Modern computing applications and components have created a need for faster access memory. Recently, SDRAM has gained popularity. Unlike older asynchronous memory systems, data transfers from and to SDRAM are at a clocked rate. As the timing of SDRAM is very predicable, data can be transferred at a much higher rate than was possible with asynchronous random access memory designs. SDRAM and SDRAM access are, for example, detailed in Micron, MT46V32M4, MT46V16M8, and MT46V8M16 data sheets, the contents of which are hereby incorporated by reference.
At present, however, SDRAM is still quite costly. As a result, there is frequently a need in dedicated high performance memory systems to trade-off memory bandwidth (i.e. bits transferred per second) and storage capacity, for cost.
Typically, higher memory bandwidth may be achieved by transferring data in data units having increased bit sizes or at a higher rate.
So, for example, data transfer in data units of thirty-two bits can reach twice the memory bandwidth of data transfer in data units of sixteen bits. This, however, requires SDRAM modules having a larger data bus or multiple SDRAM modules interconnected to span accessed memory. Such re-configuration of memory to provide data units of increased bit size is often complex and requires chip and software re-design. Moreover, not all applications require the data unit bit size, that provides the memory bandwidth
Similarly, memory may be accessed at higher speeds. Indeed, memory system design has witnessed a steady increase in bus speeds. In fact, modern SDRAM manufacturing and design techniques are producing SDRAM modules having a high density and manufactured to tight tolerances, that often allow memory access in excess of conventional memory bus speeds. However, memory accessing devices such as central processing units (CPUs), graphics processors, video processors, direct memory access (DMA) controllers and the like are typically designed to operate at the more conservative, conventional memory bus speeds, and therefore do not access the SDRAM at these higher rates.
Accordingly, there is a need for a simple interface that allows interconnection of a memory access device to SDRAM that provides flexibility in how interconnected random access memory may be configured, and the bandwidth with which the memory may be accessed.